Design of a low power and high performance digital multiplier using a novel 8T adder

Low power VLSI circuits have become important criteria for designing the energy efficient electronic designs for high performance and portable devices .The multipliers are the main key structure for designing an energy efficient processor where a multiplier design decides the digital signal processors efficiency.Multiplier is the most commonly used circuit in the digital devices. Multiplication is one of the basic functions used in digital signal processing. Full Adder is the main block of power dissipation in multiplier. So reducing the power dissipation of full adder ultimately reduces the power dissipation of multiplier. In this paper a XNOR gate using three transistors has been presented. A single bit full adder using eight transistors has been designed using XNOR cell, which shows power dissipation of 620.5μW. A 4x4 Wallace tree multiplier has been implemented by using the proposed 8T adder. Simulations have been carried out by using cadence tool based on gpdk180nm CMOS technology Keywords-CMOS, exclusive-OR (XOR), exclusiveNOR (XNOR), full adder, low power, multiplier.